1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus broadly used in image input devices of, for example, video cameras, digital still cameras, and image scanners.
2. Related Background Art
In recent years, in order to achieve higher resolution, reduction of the cell size of photoelectric conversion elements using miniaturization processes is being pursued vigorously, but the accompanying loss of photoelectric conversion signal output has drawn attention to amplification-type solid-state image pickup apparatuses capable of amplifying and outputting photoelectric conversion signals. Such amplification-type solid-state image pickup apparatuses include MOS-type, AMI, CMD, BASIS and the like. Among these, the MOS-type accumulates an optical carrier generated at a photodiode in a gate electrode, and based on a drive timing from a scan circuit, performs electric charge amplification to output the potential change to an output portion. In recent years, among the MOS-types, attention is being given particularly to a CMOS-type solid-state image pickup apparatus where the whole configuration including the photoelectric conversion portion and its peripheral circuitry is formed using CMOS processes.
FIG. 12 shows a block diagram of a conventional CMOS-type solid-state image pickup apparatus. In FIG. 12, reference numeral 1 denotes a pixel portion, reference numeral 2 denotes a vertical scanning circuit block for performing vertical scanning, symbols D11-D33 denote photodiodes, symbols M211-M233 denote reset MOSs for resetting electric charges of the photodiodes, symbols M311-M333 denote amplifications MOSs for amplifying the electric charges of the photodiodes, symbols M411-M433 denote selection MOSs for selecting the rows, symbols V1-V3 denote vertical signal lines, reference numerals M51-M53 denote load MOSs serving as loads of the amplification MOSs, symbol M50 denotes an input MOS for setting a constant current flown to the load MOSs, and reference numeral 5 denotes a voltage input terminal for setting a gate voltage of the input MOS.
Below, explanation will be made of the operation. When light enters the photodiodes D11-D33, photo-signal charges are generated and accumulated. The reading of the signals is performed by the vertical shift resistor 2 which vertically scans rows to read out signals to the vertical scanning lines V1-V3 in sequence on a row basis. First, when the first row is selected, PSEL connected to the gates of the selection MOSs M411-M431 changes to a high level, and the amplification MOSs M311-M331 become active. As a result, the signals from the first row are read out to the vertical signal lines V1-V3. Next, PRES 1 connected to the gates of the reset MOSs M211-M231 changes to a high level and the electric charges accumulated in the photodiodes D11-D31 are reset. Next, the second row is selected and the signals of the second row are similarly read out to the vertical signal lines V1-V3. The third and subsequent rows are similarly read out sequentially to the vertical signal lines V1-V3.
However, according to the above-mentioned reading operation, the greater the photo-signal becomes, the lower the voltages of the vertical signal lines V1-V3 become. Further, since the vertical signal lines V1-V3 are connected to the drains of the load MOSs M51-M53, the electric current values of the load MOSs change due to a channel length modulation effect of the MOS transistors when the voltages on the vertical signal lines change. Therefore, the electric current flowing to a common GND line 4 during read-out of a certain row changes depending on the number of pixels into which light enters become, or depending on the amount of light that has entered them.
On the other hand, due to limitations of chip size and the like, the GND line 4 can only have a line width of a limited value, and thus it has a certain impedance. Further, since the value of the constant current flowing to the load MOS is set by applying an input voltage 5 between the gate of the input MOS M50 and an absolute GND (for example, a ground potential of an external board), the value of the set current changes due to a voltage drop that is determined by the impedance of the GND line 4 and the current that is flowing. Therefore, the greater the number of pixels into which light enters becomes, or the greater the amount of incident light becomes, the less the voltage drop in the GND line 4 becomes and the greater the set current of the load MOS becomes.
In a case where a strong light has entered only some of pixels in a given row, the current value of the load MOSs increases also in pixels where the light does not enter (i.e., dark pixels), and thus the voltage between the gate and the source of its amplification MOS increases. This phenomenon causes the output voltages of the dark pixels to differ between rows which include pixels where strong light enters and rows which do not, and thus there is a problem that a whitish strip occurs on the left and right of a spot on an image upon which a strong spot light is made incident. Further, in a solid-state image pickup apparatus having an optical black (OB) pixel, the output voltages from the dark pixels and the OB pixels differ between a line which includes pixels into which strong light enters and a line which does not, and thus a similar problem described above occurred.